This invention relates to High-Density Interconnects for active chips, and more particularly to ameliorating the effects of radio-frequency (RF) radiation by incorporation of a molded, electrically conductive shield which is also used as a boundary for application of liquid encapsulant.
High density interconnect assemblages such as those described in U.S. Pat. No. 4,783,695, issued Nov. 8, 1988 in the name of Eichelberger et al., and in numerous other patents, are finding increased usage. In one form of HDI assemblage, a dielectric substrate such as alumina has a planar surface and one or more wells or depressions. Each well or depression extends below the planar surface by the dimension of a component which is to become part of the HDI assemblage. The component is typically an integrated circuit, having its electrical connections or contacts on an upper surface. Each component is mounted in a well dimensioned to accommodate the component with its contacts in substantially the same plane as the planar surface of the substrate. The components are typically held in place in their wells or depressions by an epoxy adhesive. A layer of dielectric material such as Kapton polyimide film, manufactured by DuPont of Wilmington, Del., is laminated to the devices using ULTEM polyetherimide thermoplastic adhesive, manufactured by General Electric Plastic, Pittsfield, Mass., which is then heat-cured at about 260xc2x0 to 300xc2x0 C. in order to set the adhesive. The polyetherimide adhesive is advantageous in that it bonds effectively to a number of metallurgies, and can be applied in a layer as thin as 12 micrometers (xcexcm) without formation of voids. Further, it is a thermoplastic material, so that later removal of the polyimide film from the components is possible for purposes of repair by heating the structure to the glass transition temperature of the polyetherimide while putting tension on the polyimide film.
Another known method for making HDI modules includes applying the chips, electrode-side-down, onto an adhesive-faced dielectric layer. The chips are then encapsulated in a rigid material, which in one embodiment is Plaskon, an epoxy material, to form a rigid molded-chip-plus-dielectric-sheet piece. The electrical interconnections are made by means of laser-drilled vias through the dielectric sheet, followed by patterned deposition of electrically conductive metallization.
A method according to an aspect of the invention is for making a multi-chip module including an electrically conductive enclosure. The method comprises the steps of procuring a planar flexible insulating substrate defining a front and rear surfaces, and selecting at least one solid-state or active chip defining a plurality of electrical connections lying in a plane. The at least one solid-state chip is disposed at a selected location on the front surface of the insulating substrate, with the plane of the electrical connections facing the insulating substrate. A generally planar electrically conductive enclosure is procured. This enclosure defines first and second broad surfaces and at least one aperture extending from the first broad surface to the second broad surface. The enclosure so procured may be made by a molding process, and in a preferred embodiment is made from molded graphite or carbonaceous material. The first broad surface of the enclosure is applied to the front surface of the insulating substrate with the aperture surrounding the location. Hardenable liquid encapsulant is applied to the front surface of the insulating substrate through the aperture in the enclosure, to a depth sufficient to encapsulate at least a portion of the at least one solid-state chip. Electrical interconnections are made to at least some of the electrical connections of the at least one solid-state chip from the second surface of the insulating substrate.
In a particular mode of the method according to an aspect of the invention, the flexible insulating substrate may be rendered planar by tensioning. In another mode, the step of applying the first broad surface of the enclosure to the front surface of the insulating substrate with the aperture surrounding the location may precede the step of disposing the at least one solid-state chip at a selected location on the front surface of the insulating substrate. The step of making interconnections may include the steps of forming apertures through the insulating substrate to at least some of the electrical connections to thereby expose at least portions of the electrical connections, and metallizing of the apertures and the exposed portions of the electrical connections.
For some purposes, a variant of a mode of a method according to an aspect of the invention relating to applying the enclosure may include the step of laminating the enclosure to the front surface of the insulating substrate. In one manifestation, the step of applying the enclosure includes the steps of (1) applying adhesive to at least a portion of one of (a) the first broad surface of the enclosure and (b) the first broad surface of the insulating substrate, and (2) applying the first broad surface of the enclosure to the first surface of the insulating substrate, with at least a portion of the adhesive lying therebetween.
The enclosure may define a plurality of apertures extending from the first to the second broad surfaces. Similarly, the enclosure may bear a surface metallization over some or all of its surface. A further step may include the making of electrical connections through the insulating substrate to the enclosure.